Gartner Research

Market Trends: ASIC and ASSP Chip Design Start Trends, Worldwide, 2013

Published: 16 August 2013

ID: G00246635

Analyst(s): Ganesh Ramamoorthy

Summary

The pace of leading edge process node adaption is slowing down. In a bid to save design costs, chip designers are using mature and mainstream process nodes for new designs. This, along with the continuing decline in overall chip design starts, means a sharper decline for leading edge design starts.

Table Of Contents

Introduction

  • Overall Design Starts Will Decline by 2% in 2013
  • ASIC Design Starts Continue to Decline Faster Than ASSP Design Starts
  • FPGA Designs Continue to Compete for Low- and Mid-Volume ASIC Sockets

Market Trend

  • ASIC Design Value, Complexity and Volume Continue to Grow
  • Market Structure Trend
    • Automotive, Compute and Wireless Device Segments Cushion Decline Rate of Design Starts
  • Buyers Trend
    • Rising Design Cost and Complexity, Design Cycle Time and Performance Requirements Change Chip Design Approach
  • Regional Trend
    • Asia/Pacific Continues to Dominate New ASIC and ASSP Chip Design
  • Technology Trend
    • Mature and Mainstream Designs Hold Steady as Cost of Leading Edge Designs Skyrockets

Contrarian View

  • Platform Design Methodology and IoT May Help Reverse Declining Design Start Trend

Vendors to Watch

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