Gartner Research

Forecast: ASIC and ASSP Chip Design Starts, Worldwide, 2015 Update

Published: 21 January 2015

ID: G00271887

Analyst(s): Ganesh Ramamoorthy

Summary

The rate of decline of ASIC and ASSP chip design starts is slowing, thanks to new designs targeting automotive and industrial applications — driven mainly by the growing hype around the Internet of Things (IoT), which will help to slow the pace of decline through 2019.

Table Of Contents

Forecast Data

Analysis

  • ASIC/ASSP Chip Design Starts Continue Declining Trend
  • Driven by IoT, Industrial Applications Will See More New Designs
  • Through 2019, 65/55-nm Will Be the Mainstream Process Node
  • ASIC Design Value, Complexity and Volume Continue to Grow

Assumptions

  • Total Chip Design Spend
  • Cost of Design Tools
  • Cost and Supply of Engineers
  • Engineer Productivity
  • Rate of Functional Integration
  • Feature and Function Integration Demand

Methodology

  • Market Model
    • Forecast Components
    • Influencing Factors
    • Connections

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