Gartner Research

Best Practices for ASIC Chip Design by System/OEM Companies

Published: 18 October 2017

ID: G00342315

Analyst(s): George Brocklehurst , Samuel Wang , Jon Erensen


Building your own semiconductor chip often means defining your own electronic specifications and creating product differentiation. Technology business unit leaders must develop a strategy focused on the areas summarized in this report.

Table Of Contents
  • Key Challenges



  • (A) Ensuring Semiconductor Experience Throughout the Complete Product Team Is the Biggest Challenge of Chip Projects
    • Recruit or Acquire an Experienced Semiconductor Team to Handle Critical Chip Tasks
    • Plan It Right; a Correct Chip Architect Is Pivotal for System Integration Benefits
    • Execute It Right; Manage Projects by the Semiconductor Team From Design to Verification and Test
  • (B) The Core Value of System/OEM Companies Is Knowledge of System Products and the Ability to Tailor ASIC Chips to Their Specific Needs
    • Require System and Software Teams to Be Involved in Defining the ASIC Device Specs and Identifying Areas of Potential Differentiation From Key Competitors
    • Align All Teams in the Product Roadmaps to Assure Long-Term Success
  • (C) Requirement Alignment, Configurability, IP Reuse and Yield Binning Strategies Are Essential in Maximizing Return From a Limited Internal Market
    • Leverage the ASIC Design Across Many Electronic Equipment Categories to Maximize the Return on the Chip Design Investment
    • Use Configurable Chip Strategies to Improve Adoption Across Multiple Product Lines
    • Include Redundancy Blocks in Chips to Maximize the Wafer Yield; Use or Sell Partially Good Die Whenever Possible
    • Make Reuse of IP Blocks to Save Time and Cost for Future Chip Projects
  • (D) Precise Execution Supported by the Right Business Partners Assures Fast Time to Market
    • Choose Vendors and Partners Only With a Proven Track Record, Even at Higher Costs
    • Execution by Goal Setting and Routine Project Reviews With Good Transparency Internally and Externally
    • Collaborate With Foundries and Semiconductor Assembly and Test Services (SATS) Vendors to Understand the Requirements of Design Rules, IP and Testability Issues Related to Advanced Packages

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